In a conventional bit map display controlling apparatus of this type, addresses of a video memory are assigned sequentially in the order of raster scanning, and a display controller accesses the video memory in the order of addresses to perform a refresh display of the contents of the video memory.
Addresses of the video memory as seen from a central processing unit (hereinafter called a CPU) are also assigned in the above-described manner. FIG. 4 shows the structure of a conventional bit map display controlling apparatus. In FIG. 4, a display controller 1 generates addressess a2 for reading to the video memory 2 sequentially in the order of raster scanning and supplies them to a video memory 2 storing the laster scan type display contents. The video memory 2 outputs display data d2 in the order of raster scanning.
CPU 3 accesses, when necessary, the video memory 2 fixedly assigned with the addresses in the order of raster scanning, and changes the data in the video memory 2 to a data d1.
FIG. 5 shows an example of an address map of the video memory 2 of a conventional bit map display controlling apparatus. This example of FIG. 5 is applied to a bit map display controlling apparatus wherein 1024 dots are scanned in the horizontal direction, and 512 dots are repeatedly scanned (having 512 scan lines) in the vertical direction. Byte addresses are sequentially assigned in the horizontal direction on the 8 dots (bits) unit basis. Numbers in FIG. 5 represent the byte addresses.
The numbers of dots in the horizontal and vertical directions may vary depending upon a bit map display controlling apparatus. However, in general, the address assignment of a conventional bit map display controlling apparatus is in the order of raster scanning such as shown in FIG. 5.
The above-described conventional bit map display controlling apparatus is, however, associated with a problem that in writing data into the video memory under control of CPU 3, an address translation calculation to be executed by a program may sometimes become complicated depending upon the contents of the data, because the addresses of the video memory 2 are fixedly assigned, thereby increasing the processing time and the quantity of program.
Consider for example the case where a program of CPU 3 reads a character "A" composed of 8 bits in the horizontal direction and 8 bits in the vertical direction as shown in FIG. 3(a), from a character generator at addresses from 0 to 7, and writes the character data in the video memory at addresses from 0 to 896 at the interval of every 128-th address. In this case, although the consecutive 8 bytes are accessed for reading the data on the side of the character generator data writing on the side of the video memory requires an address addition calculation for each byte by using a program, because the corresponding addresses of the video memory are not consecutive.
The present invention solves such conventional problems and aims at providing a bit map display controlling apparatus wherein in writing data in a video memory by using a program of CPU, the addresses generated by a display controller sequentially in the order of raster scanning can be translated as desired depending upon the contents of the data so as to satisfy the program, thereby reducing the load on the program of CPU.